Achieving proper operation of a memory circuit, such as a DRAM, typically requires an initial pause of 200 .mu.sec followed by a minimum of eight initialization cycles after reaching the full V.sub.CC level. Within the generally specified power-up pause of 200 .mu.sec, reliable DRAM operation demands on-chip generated back bias voltage (V.sub.BB). Providing the needed V.sub.BB reduces junction capacitance, reduces substrate leakage and prevents forward biasing of junctions. Generating a deep V.sub.BB level within the specified power-up, however, becomes difficult at low operating voltages (e.g., approximately 3.3V). This is particularly true if the V.sub.BB load capacitance is high, such as is the case for sub-micron technologies and higher DRAM densities. For instance, the typical V.sub.BB load capacitance of a 16 Mb DRAM employing trench capacitor cells as storage elements is about 240 nf.
One type of circuit design for initializing and enabling peripheral circuits on a memory chip generates internally a positive pulse RID(RAS.sub.-- Input Disable). In this circuit, RID is designed to go positive as soon as power-on conditions are detected and reset when V.sub.BB reaches a preset level. The resetting is usually accomplished by means of an analog sensor, which detects when the V.sub.BB level is 2 Vtn below-ground. For example, TABLE 1 documents RID trip points for the 16 Mb shrink (16 MS) low voltage (3.3V) DRAM fabricated using 0.5 .mu.m technology. As TABLE 1 shows, RID reset is marginal to the power-up specification of 200 .mu.s at 2.6V, 100.degree. C. and using a MSIG (minus sigma) process model.
TABLE 1 ______________________________________ 16MS SIMULATION RESULTS SIMULATION CONDITIONS/MODEL RID TRIP POINT VBB @ RID ______________________________________ 2.6V, 100C.vertline.MSIG 203 us -0.89V 4.0V, -10C.vertline.PSIG 45 us -1.12V ______________________________________
Of particular importance is the fact that if RID is not reset within the power-up spec time, then the device operation cannot be guaranteed.
In other words, this method uses RID to manipulate V.sub.BB pumping during power-up in the memory device. RID is made a function of V.sub.BB, through a predetermined level sensor. V.sub.BB pumping starts as soon as power-on is detected and stops after RID is reset. Such a scheme may be inadequate for low voltage operations, because at 16 MB densities, higher substrate capacitances result. Thus, V.sub.BB may not reach a deep enough level to reset RID. This will keep the device in initialization mode, and prohibit normal memory device operation.
One method to reset RID expeditiously is to pump harder the V.sub.BB, SO that RID reset is not marginal to spec. Usually, V.sub.BB pumping during power-up is stopped after RID is reset. This method extends pumping beyond RID reset so that the V.sub.BB level is deep on power-up. As the process models/operating conditions change, if pumping is extended uncontrolled, V.sub.BB becomes too deep and may adversely affect memory device operation.